Communication networks are continuing to grow, with current and projected rates in excess of 30% annualized increase in bandwidth. Such growth rates imply network bandwidth is doubling approximately every two-and-a-half years. At the same time, network hardware cost, space, and power consumption allocations are staying roughly flat. Equipment manufacturers must, therefore, deliver substantial continuous reductions in per-bit metrics related to cost, space, and power. Conventional network architectures utilize various layers in construction with higher layers providing more functionality, but at the expense of increased cost, size, and power. For example, at Layer 3, Internet Protocol (IP) router power consumption is dominated by packet storage and packet processing as described by A. Vishwanath et al., “Estimating the energy consumption for packet processing, storage and switching in optical-IP routers,” OFC 2013, OMA3A.6. Layer 1 Optical Transport Network (OTN)-type circuit switching eliminates packet storage and substantially simplifies processing. Therefore, the remaining switching energy becomes dominant in OTN and other time division multiplexing (TDM) techniques.
Layer 0 has been largely implemented in the optical domain, and with optical wavelength switching functions. This layer operates on signal “flows,” which are defined by their large granularity and by the momentary data loss during reconfiguration operations. These wavelength flows are configured only on capacity turn-up, and remain generally static thereafter in current networks, due to complex, large and slow optical wavelength switching fabrics. The dynamic optical switching function is further complicated by the noisy and analog nature of optical signal propagation, and by large uncertainties in predicting optical signal propagation performance. However, optical switching does provide low power consumption as it operates on very large bandwidth flows (i.e., wavelengths).
Conventionally, flow-based switching at Layer 0, i.e., wavelength switching, has been performed in the optical domain via Reconfigurable Optical Add/Drop Multiplexer (ROADM) devices which can use various techniques such as Wavelength Selective Switches (WSS). Disadvantageously, optical domain processing does not have the cost-reduction benefits of electronic domain processing. However, conventional techniques for electronic domain flow-based switching are costly and consume high power. As networks continue to grow, there is a need for dramatic cost, size, and power reductions in flow-based switching at high bandwidth granularity. At the same time, switching should be performed in the electronic domain preserving all the attendant advantages of switching predictability, ease of viable path computation, switching speed, etc.
Referring to FIGS. 1-4, in various exemplary embodiments, conventional techniques for flow-based cross-point switches can be divided into several categories. FIG. 1 illustrates a bipolar transistor current mode logic (CML) 4:1 multiplexer 10 which is an active switch based on CML multiplexers. Input signals are first fanned-out to a set of multiplexers. The multiplexer connected to a particular output selects which input is connected to the corresponding output. Level 1 provides active data switching, and Level 2 and 3 provide input selection (i.e., addressing). This is described in J. W. Kim, “Ge High Speed Cross-point Switch for Digital Signal Router and Phased Array Antenna Systems,” Ph.D. Thesis, Rensselaer Polytechnic Institute, Troy, N.Y., July 2009 (www.ecse.rpi.edu/frisc/theses/KimThesis/Kim_Thesis 2009.pdf). FIG. 2 illustrates a BiCMOS 4:1 multiplexer 20 which can lower power consumption relative to the bipolar CIVIL 4:1 multiplexer 10 by replacing the “address” Level 2 and 3 with field-effect transistor (FET) based devices since their switching speed can be substantially lower than the data rate. BiCMOS is an integration of bipolar junction transistors and Complementary metal-oxide-semiconductor (CMOS) transistors. However, both of the multiplexers 10, 20 draw substantial amounts of continuous current and are therefore quite high in power consumption. For example, a commercial version of such architecture in a 160×160 cross-point switch at 6.5 Gbps consumes approximately 23 W.
FIG. 3 is a CMOS 8:1 multiplexer 30 based on AND gates. This is described, for example, in U.S. Pat. No. 4,849,751 to Barber et al. entitled “CMOS Integrated circuit digital crossbar switching arrangement.” The CMOS 8:1 multiplexer 30 requires significant input data parallelization to a wide bus as CMOS gates cannot run directly at high data rates such as 10 Gbps, 28 Gbps, etc. Also, deep submicron CMOS still consumes substantial power even in a standby state due to leakage currents, and total power consumption for the circuit can be quite significant.
FIG. 4 is a FET-based through switch 40 (M2 and M4) with shunts for isolation (M1 and M3). The FET transistors can be used as direct ON/OFF switches for controlling the connection path of analog Radio frequency (RF) signals. There are several issues with such an approach, which include fairly high insertion loss of ˜2 dB for the configuration shown in FIG. 4, somewhat limited power handling capability, and generation of nonlinear harmonics within active devices which have signal corrupting potential.
RF MEMS switches have a potential for very low insertion losses, of the order of 0.5 dB and below, high RF isolation, pure linear operation, good power handling capability, etc. The complexity of such switch matrixes has so far been rather limited in size, mostly due to the limited needs of the application spaces for which they were designed: switched RF filters, spectral band switching in cell phones, and antenna switching. The largest cross-point array known to the inventors is a 20×20 one developed for automating main distribution frames in copper-wire telecom networks as described in Braun et al. “Single-chip MEMS 5×5 and 20×20 double-pole single-throw switch arrays for automating telecommunication networks,” J. Micromechanics and Microengineering, vol. 18, no 1. The 20×20 array occupied an area of 14×10 mm2 and exhibited ON-state series resistance in the range of 0.08 to 2.33 Ohm.